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IDT74FCT163344CPC

3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER

Integrated Device Technology 

IDT74FCT163344/A/C

3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER

INDUSTRIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

V CC

6v

Open

VIN

Pulse

Generator

D.U.T.

RT

V OUT

50pF

CL

500Ω

500Ω

GND

SET-UP, HOLD, AND RELEASE TIMES

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

6V

Enable Low

Disable High

GND

Enable High

All Other Tests

Open

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

3v16-link

DATA

INPUT

TIMING

INPUT

PRESET

CLEAR

ETC.

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

tH

tREM

tSU

tH

3V

1.5V

0V

PULSE WIDTH

3V

1.5V

0V

3V

1.5V

L O W -H IG H -L O W

PULSE

0V

tW

3V

1.5V

0V

H IG H -L O W -H IG H

PULSE

1.5V

1.5V

PROPAGATION DELAY

SAME PHASE

INPUT TRANSITION

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

tPLH

tPLH

tPHL

tPHL

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

OUTPUT SKEW - tSK (x)

INPUT

OUTPUT 1

OUTPUT 2

tPLH1

tPHL1

tSK(x)

tSK(x)

tPLH2

tPHL2

VIH

VT

0V

VOH

VT

VOL

VOH

VT

VOL

NOTES:

tSK(x) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

ENABLE AND DISABLE TIMES

ENABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZL

S W ITC H

6V

tPZH

OUTPUT

NORMALLY

H IG H

S W ITC H

GND

D IS A B L E

tPLZ

3V

1.5V

tPHZ

1.5V

0V

0.3V

0.3V

3V

1.5V

0V

3V

VOL

VOH

0V

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

3. If Vcc is below 3V, input voltage swings should be adjusted not to

exceed Vcc.

6

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