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IDT74FCT163344APV8
(Rev.:2004)

3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER

Integrated Device Technology 

IDT74FCT163344A/C

3.3V CMOS ONE-TO-FOUR ADDRESS/CLOCK DRIVER

TEST CIRCUITS AND WAVEFORMS

6v

V CC

Open

VIN

Pulse

Generator

D.U.T.

RT

VOUT

50pF

CL

500Ω

500Ω

GND

Test Circuits for All Outputs

INDUSTRIAL TEMPERATURE RANGE

SWITCH POSITION

Test

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other Tests

Switch

6V

GND

Open

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

DATA

INPUT

TIMING

INPUT

PRESET

CLEAR

ETC.

tSU

tH

tREM

PRESET

CLEAR

CLOCK ENABLE

ETC.

tSU

tH

Set-up, Hold, and Release Times

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

LOW-HIGH-LOW

PULSE

0V

tW

3V

1.5V

0V

HIGH-LOW-HIGH

PULSE

Pulse Width

1.5V

1.5V

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

OUTPUT

tPLH

tPHL

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V

0V

VOH

1.5V

VO

L

3V

1.5V

0V

Propagation Delay

INPUT

OUTPUT 1

OUTPUT 2

tPLH1

tPHL1

tSK(x)

tSK(x)

tPLH2

tPHL2

VIH

VT

0V

VOH

VT

VOL

VOH

VT

VOL

tSK(x) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

ENABLE

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

tPZ

L

SWITCH

6V

tPZH

OUTPUT

NORMALLY

HIGH

SWITCH

GND

DISABLE

tPLZ

3V

1.5V

0.3V

tPHZ

1.5V

0V

0.3V

3V

1.5V

0V

3V

VOL

VOH

0V

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.

6

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