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IDT74FCT163601PA

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

Integrated Device Technology 

IDT74FCT163601/A

3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS

COMMERCIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION

V IN

Pulse

Generator

V CC

D.U.T.

RT

V OUT

50pF

CL

500Ω

500Ω

6V

Open

GND

Test

Open Drain

Disable Low

Enable Low

Switch

6V

Disable High

Enable High

GND

All Other tests

Open

DEFINITIONS:

3251 tbl 08

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

3251 lnk 04

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA

INPUT

tSU

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

ETC.

tH

tREM

tH

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3251 lnk 05

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

1.5V

tW

1.5V

3251 lnk 06

PROPAGATION DELAY

ENABLE AND DISABLE TIMES

ENABLE

DISABLE

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

3V

1.5V

0V

VOH

CONTROL

INPUT

tPZL

3V

1.5V

0V

tPLZ

OUTPUT

1.5V

OUTPUT

3V

3V

tPLH

tPHL

VOL

NORMALLY

LOW

SWITCH

6V

1.5V

0.3V VOL

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V

0V

3251 lnk 07

OUTPUT

NORMALLY

HIGH

tPZH

SWITCH

GND

tPHZ

1.5V

0V

0.3V VOH

0V

3251 lnk 08

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

3. If VCC is below 3V, input voltage swings should be adjusted not to

exceed VCC.

5.9

6

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