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XRD64L14AIQ

3.3V CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter with 4:1 Input Analog Multiplexer

Exar Corporation 

XRD64L14

THEORY OF OPERATION

VIN Analog Input

This part has a switched capacitor type input circuit. The

input impedance changes with the phase of the input

clock. VIN is sampled at the low to high clock transition

and the digital data changes at the low to high clock

transition. The diagram Figure 4. shows an equivalent

input circuit.

AVDD

VIN

AGND

100Ω CLK

18pF 100Ω

5pF

CLK

VRT + VRB +

1.5pF

CL

2

−

Figure 4. Equivalent Input Circuit

OFW Overflow (Output)

This signal indicates when the Analog Input (VIN) goes

above VRT. The pin is normally at a low logic level. When

VIN > VRT, OFW will go high and the data bits (DB0 – DB9)

will show full scale (i.e. all 1s).

OE Output Enable (Input)

This signal controls the 3-state drivers on the digital

outputs DB0 – DB9 and OFW. During normal operation

OE should be held low so that all outputs are enabled.

When OE is driven high DB0 – DB9 and OFW go into high

impedance mode. This control operates asynchronous to

the clock and will only control the output drivers. The

internal output register will get updated if the clock is

running while the outputs are in three-state mode.

Power Supply Sequencing

There are no power supply sequencing issues if DVDD

and AVDD of the XRD64L14 are driven from the same

supply. Best parametric results, however, are obtained

when DVDD and AVDD are driven from separate supplies.

When DVDD and AVDD are driven separately, AVDD must

come up at the same time or before DVDD, and go down at

the same time or after DVDD. If the power supply

sequencing in this case is not followed, then damage may

occur to the product due to current flow through the

source-body junction diodes between DVDD and AVDD.

Logic Output Interface

The digital output drive circuitry of the XRD64L14 was

designed to operate separately from the analog supplies.

The DVDD pin of the XRD64L14 is a separate power

supply dedicated to the logic output drivers. DVDD is not

connected internally with any of the other power supplies.

Figure 5. illustrates the power supply circuity of the

XRD64L14.

DVDD and DGND connect directly to the digital logic

power of the user’s system isolating the analog and digital

power supplies and grounds. DGND is not common to the

XRD64L14 substrate. The XRD64L14 substrate is

common only to the packages’ GND pins. See the power

supply sequencing section if AVDD and DVDD are

powered separately.

AVDD

Source–body junction

diode

between DVDD

& AVDD

DVDD

A/D Circuit

DB(0-9)

& OFW

OE

DBO-DB9

OFW

0

Enabled

Enabled

1

Three-Stated

Three-Stated

Table 1. Output Enable

Rev. 1.00

Source–body junction

AGND diode between DGND

& AGND

DGND

Figure 5. XRD64L14 ADC Power Supply Circuit

Allows Separate AVDD & DVDD and Separate

AGND & DGND

7

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