BL7431A Просмотр технического описания (PDF) - Shanghai Belling Co., Ltd.
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BL7431A Datasheet PDF : 4 Pages
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BL7431A 256-Bit EEPROM Logical
Encrypted Chip
Read/Write Operation
Reading Operation
The address counter inside the chip use bit as counter-unit, at every clock’s rising edge, it
increases 1. At the falling edge of every clock, data in current address will be sent to I/O port.
When CLK is high and RST also is high, the address counter will be cleared to zero.
tR
RST
td1
tr
td2
tf
tH
CLK
td3
IO
DO0
tL
td4
DO1
Add
A0
A1
A2
Address reset and data output
RST
td5
CLK
ts
td6
td7
tHW
Add n
n+1
n+2
IO n
n+1
n+1
writing operation timing diagram
Writing Operation
When RST is high and CLK is low, “R” flag inside the chip will be set. Under such condition, when
next CLK arrived, the chip will enter writing process with address counter no increasing. During
writing operation, CLK keep high. When writing operation is finished, at the falling edge of CLK,
address counter will be effective again, at the same time, “R” flag will be reset. To chip
manufacture area, “R” flag has no use.
Erasing Operation
When writing operation is finished, if again comes a “RST pulse” and CLK keep low, “R” flag will
be set again and the chip enter erasing status. Such operation to any bit of same byte has same
effect. To PROM area, erase is invalid.
RST
CLK
tS
td6
tHW
tS
td7
tHE
Add
n
n+1
IO n
n
n
Erasing operation timing diagram
Power on reset
Address is reset after power on. At this time, RST must keep high than one CLK period. When
RST goes low, data in address zero will be sent to I/O port.
About Comparison of Transmission Password
Password comparison must be executed immediately after write “0” operation
RST
CLK
tHW
ADDRESS 0
I/O
1
EC(LSB-1)
~EC(MSB-1)
D0
EC bit addr
Bit output Write one bit EC
80
81
82
td8
td9
D8
D8
D8
0
1
2
Comparison of Transmission Password timing diagram
http://www.belling.com.cn
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Total 4 Pages
103 104
td10
D103
8/16/2006
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