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RS5C338A-E2

3-WIRE SERIAL INTERFACE REAL-TIME CLOCK ICS WITH VOLTAGE MONITORING FUNCTION

RICOH Co.,Ltd. 

R×5C338A

Considerations in Using Oscillation Halt Sensing Circuit

Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:

1) Instantaneous power-down on the VDD

2) Condensation on the crystal oscillator

3) On-board noise to the crystal oscillator

4) Applying to individual pins voltage exceeding their respective maximum ratings

In particular, note that the XSTP bit may fail to be set to 1 in the presence of any applied supply voltage as

illustrated below in such events as backup battery installation. Further, give special considerations to prevent

excessive chattering to power supply.

VDD

< Supply Voltage Sensing Circuit >

The supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per

second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.6 volts for the VDSL bit setting of 0

(the default setting) or 1, respectively, in the control register 2, thus minimizing supply current requirements as

illustrated in the timing chart below. This circuit suspends a sampling operation once the VDET bit is set to 1 in the

control register 2.

VDD

XSTP

Internal initialization period

(1 or 2 seconds)

Sampling operation by supply voltage

monitoring circuit

VDET

(D6 at address Fh)

7.8ms

1s

Setting 0 to XSTP

and VDET bits

Threshold voltage

of 2.1 or 1.6 volts

Setting VDET bit to 0

33

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