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XRD9812ACQ

3-Channel 10/12-Bit Linear CCD & CIS Sensor Signal Processors

Exar Corporation 

XRD9810/12

ELECTRICAL CHARACTERISTICS (CONT’D)

Test Conditions: AVDD=DVDD=5.0V, ADCCLK=6MHz, TA=25°C unless otherwise specified.

Symbol Parameter

Min.

Typ.

Max.

Unit Conditions

TIMING SPECIFICATIONS

tcr3

3--Channel Conversion Period

400

ns

tcr1

1--Channel Conversion Period

166

ns

tpwb

BSAMP Pulse Width

30

ns

tbvf

BSAMP falling edge to VSAMP

70

ns

falling edge.

tvbf

VSAMP falling edge to BSAMP

70

ns

falling edge.

tvfcr

VSAMP falling edge delay from 30

ns

rising ADCCLK. (All modes ex-

cept 1 Channel S/H).

tvfcr

VSAMP falling edge delay from 70

rising ADCCLK (1 Channel S/H)

ns

Config REG #1, PB2=1, PB7=1

tpwv

VSAMP Pulse Width

30

ns

VSAMP TIMING OPTION #1

tvrcf

VSAMP rising edge delay from

15

falling ADCCLK (Note 1)

ns

tvrcr is not required,

Config REG #1, PB0=0

VSAMP TIMING OPTION #2, Config Reg #1, PB0=1

tvrcr

VSAMP rising edge delay from

15

rising ADCCLK (Note 1)

ns

tvrcf is not required

taclk

ADCCLK Pulse Width

50

ns

tcp1

ADCCLK Period (1 Ch. Mode)

166

ns

tcp3

ADCCLK Period (3 Ch. Mode)

133

ns

tstl

PGA Settling Time for accurate 70

ns

ADC Sampling

ts

SYNCH Rising, Falling Setup

15

ns

th

SYNCH Rising, Falling Hold

15

ns

tap

Aperture Delay

5

ns

Rev. 1.00

10

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