AV9172-03CN16 Просмотр технического описания (PDF) - Integrated Device Technology

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AV9172-03CN16

Low Skew Output Buffer

Integrated Device Technology 

AV9172

Pin Configuration

Functionality Table for AV9172-03

CLKIN Input Frequency=X, input range is 10 to 50 MHz.

EN2 INV# Q0 Q1 Q2 Q3 Q4 Q5

0

0 2X 2X 2X 2X 2X 2X

1

0 2X 2X 2X 2X 2X 1X

0

1 2X 2X 2X 1X 1X 2X

1

1 2X 2X 2X 1X 1X 1X

16-Pin SOIC or 16-Pin PDIP

Example Table for AV9172-03

(33 MHz input, all frequencies in MHz.)

EN2 INV# Q0 Q1 Q2 Q3 Q4 Q5

0

0 66 66 66 66 66 66

1

0 66 66 66 66 66 33

0

1 66 66 66 33 33 66

1

1 66 66 66 33 33 33

Timing Diagram for AV9172-03

Note: The phase alignment between the 1X clock outputs and

reference clocks input will be either at a 0 or 180 degrees

offset if the 2X clock is used as the feedback signal (con-

nected to the FBIN pin). Which relationship occurs is totally

random and has the potential to change any time the device has

its VDD supply cycled off or the devices input clock

removed.

4

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