AT59C11 Просмотр технического описания (PDF) - Atmel Corporation

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AT59C11

4-Wire Serial EEPROMs

Atmel Corporation 

AT59C11/22/13

Functional Description

The AT59C11/22/13 are accessed via a simple and versa-

tile 4-wire serial communication interface. Device operation

is controlled by six instructions issued by the host proces-

sor. A valid instruction starts with a rising edge of CS

and consists of a Start Bit (logic ‘1’) followed by the appro-

priate Op Code and the desired memory Address location.

READ (READ): The Read (READ) instruction contains

the Address code for the memory location to be read. After

the instruction and address are decoded, data from the

selected memory location is available at the serial output

pin DO. Output data changes are synchronized with the ris-

ing edges of serial clock CLK. It should be noted that a

dummy bit (logic ‘0’) precedes the 8- or 16-bit data output

string.

ERASE/WRITE (EWEN): To assure data integrity, the

part automatically goes into the Erase/Write Disable

(EWDS) state when power is first applied. An Erase/Write

Enable (EWEN) instruction must be executed first before

any programming instructions can be carried out. Please

note that once in the Erase/Write Enable state, program-

ming remains enabled until an Erase/Write Disable

(EWDS) instruction is executed or VCC power is removed

from the part.

WRITE (WRITE): The Write (WRITE) instruction contains

the 8 or 16 bits of data to be written into the specified mem-

ory location. The self-timed programming cycle, tWP, starts

Timing Diagrams

Synchronous Data Timing

after the last bit of data is received at serial data input pin

DI. The Ready/Busy status of the AT59C11/22/13 can be

determined by polling the RDY/BUSY pin. A logic ‘0’ at

RDY/BUSY indicates that programming is still in progress.

A logic ‘1’ indicates that the memory location at the speci-

fied address has been written with the data pattern con-

tained in the instruction and the part is ready for further

instructions.

ERASE ALL (ERAL): The Erase All (ERAL) instruction

programs every bit in the memory array to the logic ‘1’ state

and is primarily used for testing purposes. The Ready/Busy

status of the AT59C11/22/13 can be determined by polling

the RDY/BUSY pin. The ERAL instruction is valid only at

VCC = 5.0V ± 10%.

WRITE ALL (WRAL): The Write All (WRAL) instruction

programs all memory locations with the data patterns spec-

ified in the instruction. The Ready/Busy status of the

AT59C11/22/13 can be determined by polling the

RDY/BUSY pin. The WRAL instruction is valid only at VCC =

5.0V ± 10%.

ERASE/WRITE DISABLE (EWDS): To protect against

accidental data disturb, the Erase/Write Disable (EWDS)

instruction disables all programming modes and should be

executed after all programming operations. The operation

of the READ instruction is independent of both the EWEN

and EWDS instructions and can be executed at any time.

Note: 1. This is the minimum CLK period.

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