AT49F1024A-55VC Просмотр технического описания (PDF) - Atmel Corporation

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AT49F1024A-55VC

1-megabit (64K x 16) 5-volt Only Flash Memory

Atmel Corporation 

Block Diagram

The optional 8K word boot block section includes a reprogramming write lockout feature

to provide data integrity. The boot sector is designed to contain user secure code, and

when the feature is enabled, the boot sector is permanently protected from being erased

or reprogrammed.

VCC

GND

OE

WE

CE

ADDRESS

INPUTS

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

DATA INPUTS/OUTPUTS

I/O15 - I/O0

16

DATA LATCH

INPUT/OUTPUT

BUFFERS

Y-GATING

MAIN MEMORY

(56K WORDS)

OPTIONAL BOOT

BLOCK (8K WORDS)

FFFFH

2000H

1FFFH

0000H

Device Operation

READ: The AT49F1024A is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high impedance state whenever CE

or OE is high. This dual line control gives designers flexibility in preventing bus

contention.

CHIP ERASE: When the boot block programming lockout feature is not enabled, the

boot block and the main memory block will erase together from the same Chip Erase

command (See Command Definitions table). If the boot block lockout function has been

enabled, data in the boot section will not be erased. However, data in the main memory

section will be erased. After a chip erase, the device will return to the read mode.

MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block

erase can be performed, which will erase all words not located in the boot block region

to an FFFFH. Data located in the boot region will not be changed during a main memory

block erase. The Main Memory Erase command is a six-bus cycle operation. The

address (555H) is latched on the falling edge of the sixth cycle while the 30H data input

is latched on the rising edge of WE. The main memory erase starts after the rising edge

of WE of the sixth cycle. Please see main memory erase cycle waveforms. The main

memory erase operation is internally controlled; it will automatically time to completion.

WORD PROGRAMMING: Once the memory array is erased, the device is programmed

(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be

programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming

is accomplished via the internal device command register and is a four-bus cycle

operation (please refer to the Command Definitions table). The device will automatically

generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever

occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.

Programming is completed after the specified tBP cycle time. The Data Polling feature

may also be used to indicate the end of a program cycle.

2 AT49F1024A

3415A–FLASH–11/03

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