AT48802-16QC Просмотр технического описания (PDF) - Atmel Corporation
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AT48802-16QC Datasheet PDF : 23 Pages
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AT48802
TDD Rate
R9 b7, when set low, causes the TDD rate to be normal
7500 Hz. When set high, the TDD rate is 1875 Hz. This
mode can cause the transmit signal to be 1875 Hz square
wave AM. This is useful when the handset must wake-up
and detect whether it is being signaled in a very short time.
If the PN is turned off then the receive microcontroller can
be setup as a very narrow 1875 Hz filter and detector to
decide very quickly if the base is signaling the handset. If
not, it may go back to sleep.
When in 1875 Hz TDD mode, delays and pulse widths of
RSSI, AUD T/H, AUX T/H and internal data path timing do
not change, and still work in normal specified manner, so
this mode is only for very specialized use.
Port 0
Port 0 is a general purpose register output port of the
AT48802. It is suitable for various housekeeping functions
of a telephone such as making LED indicators turn on,
driving a DTMF generator, keypad sensor, etc. This port is
accessed through R7 b0-7 and its outputs appear on pins
2 through 6 and 12 through 14 of the chip.
Test Aids
Sync Output
The SYNC pin 52 can be used to observe the timing of TX
PN epoch and/or RX PN epoch. The functionality is con-
trolled by R9 b0-1. The pulse indicates when the gener-
ators start their PN codes, which are called the epochs.
When a chip phase lock is achieved, the syncs are almost
coincident.
Alternate Port 0
General purpose output port 0 bits 0-3 can be pro-
grammed in normal operation by writing to register 7. Al-
ternate usage of these bits for engineering test purposes
is enabled and disabled by first writing the desired configu-
ration to register 13 (decimal 19). Note that in each case,
a zero bit in register 13 enables the standard configuration
for the ASIC port 0 outputs.
Table 1. Port bit 0.0 alternate usage:
P0.0
Reg 0x13 bits [3:2]
0
0
0
1
1
0
1
1
Test Selector P0.0 Function
Follows P0.0 (Reg 7 bit 0) normal
operation
Data path demodulator, receive
clock
Data path demodulator, receive
local oscillator
Data path demodulator, dump
signal (bit synchronized integrate
and dump processing)
The alternate uses of port 0.0 all deal with timing signals
associated with the phase shift keyed data path operation.
These signals are used for correctly setting the timing de-
lays associated with hardware dependent delays in the RF
and audio data circuitry. Applications using the WLI refer-
ence design are not required to adjust the timing settings
(register 12 contents).
Table 2. Port bit 0.1 alternate usage:
P0.1
Test Selector P0.1 Function
Reg 0x13 bits [5:4]
0
0
Follows P0.1 (Reg 7 bit 1) normal
operation
0
1
Data path demodulator, phase
shift keyed output
1
0
Data path demodulator,
integrator’s LSB
1
1
Data path demodulator, carrier
detector output
The alternate uses of port 0.1 all deal with timing signals
associated with the phase shift keyed data path operation.
These signals are used for correctly setting the timing de-
lays associated with hardware dependent delays in the RF
and audio data circuitry. Applications using the WLI refer-
ence design are not required to adjust the timing settings
(register 12 contents).
Table 3. Port bit 0.2 alternate usage:
P0.2
Reg 0x13 bit [6]
Test Selector P0.2 Function
0
Follows P0.2 (Reg 7 bit 2) normal
operation
1
Receive PN Sync Pulse
The alternate use of port 0.2 allows the receive PN gener-
ator synchronization pulse to be probed. Note that an ex-
ternal pin on the ASIC is also dedicated to this function,
and can be controlled by register 9 bits 0 and 1.
Table 4. Port bit 0.3 alternate usage:
P0.3
Test Selector P0.3 Function
Reg 0x13 bit [7]
0
Follows P0.3 (Reg 7 bit 3) normal
operation
1
Transmit PN Sync
The alternate use of port 0.3 allows the transmit PN gen-
erator synchronization pulse to be probed. Note that an
external pin on the ASIC is also dedicated to this function,
and can be controlled by register 9 bits 0 and 1.
2-11
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