AT25128A Просмотр технического описания (PDF) - Atmel Corporation
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AT25128A Datasheet PDF : 18 Pages
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Top quarter, top half, or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be read only. The block write protection levels
and corresponding status register control bits are shown in Table 8.
Bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and func-
tions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25128A
AT25256A
0
0
0
None
None
1 (1/4)
0
1
3000–3FFF
6000–7FFF
2 (1/2)
1
0
2000–3FFF
4000–7FFF
3 (All)
1
1
0000–3FFF
0000–7FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hard-
ware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writeable
Protected
Writeable
Protected
Writeable
Status
Register
Protected
Writeable
Protected
Protected
Protected
Writeable
READ SEQUENCE (READ): Reading the AT25128A/256A via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the read op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10).
Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the spec-
ified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be contin-
ued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to
the lowest address, allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25128A/256A, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location
8 AT25128A/256A
5088F–SEEPR–2/07
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