MB40C338PFV Просмотр технического описания (PDF) - Fujitsu

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MB40C338PFV

3 ch 8-bit 162 MSPS A/D Converter

Fujitsu 

MB40C338

s TIMING DIAGRAM

• Demultiplex Output (in-phase) Mode

VIHD

HSYNC input

VILD

VOHD

CLKB output

CLK output

VOLD

VOHD

DSYNC output

VOLD

VOHD

ADCLKA output

VOLD

VOHD

ADCLKB output

VOLD

tpd (HSYNC-CLK)

tpd (CLK-DSYNC)

tpd (CLK-ADCLK2)

ADIN input

VOHD

DA0 to DA7 output X

VOLD

VOHD

DB0 to DB7 output X

VOLD

VOHD

OF output X

VOLD

N

N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9

tAD

tpd (CLK-DATA2)

X

X

X

X

N

N+2

X

X

X

X

N+1

N+3

X

X

X

X

N

N+2

• ADIN input: Sampling at CLK rising (at CLKB falling)

• DA0 to DA7: Output (after 6 CLK + tpd (CLK-DATA2) from sampling ) at CLK rising (at CLKB falling)

• DB0 to DB7: Output (after 5 CLK + tpd (CLK-DATA2) from sampling ) at CLK rising (at CLKB falling)

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