AS7C31025C Просмотр технического описания (PDF) - Alliance Semiconductor
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AS7C31025C Datasheet PDF : 9 Pages
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AS7C31025C
®
Read cycle (over the operating range)3,9
Parameter
Read cycle time
Address access time
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE low to output in low Z
CE high to output in high Z
OE low to output in low Z
OE high to output in high Z
Power up time
Power down time
Symbol
tRC
tAA
tACE
tOE
tOH
tCLZ
tCHZ
tOLZ
tOHZ
tPU
tPD
AS7C31025C-10
Min
Max
10
–
–
10
–
10
–
5
4
–
4
–
0
5
0
–
0
5
0
–
–
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
DOUT
tOH
Data valid
Read waveform 2 (CE and OE controlled)3,6,8,9
CE
tRC1
OE
DOUT
Supply
current
tACE
tCLZ
tPU
tOE
tOLZ
50%
Data valid
tOHZ
tCHZ
tPD
50%
Notes
3
3
5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
ICC
ISB
9/20/06, v. 1.0
Alliance Memory
P. 4 of 9
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