AS7C3256A Просмотр технического описания (PDF) - Alliance Semiconductor

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AS7C3256A

3.3V 32K X 8 CMOS SRAM (Common I/O)

Alliance Semiconductor 

AC test conditions

- Output load: see Figure B

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

+3.0V

90%

90%

10%

GND

2 ns

10%

Figure A: Input pulse

®

+3.3V

Dout

350Ω

320Ω

C13

GND

Figure B: Output load

AS7C3256A

Thevenin equivalent

168Ω

Dout

+1.72V

Notes

1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but not 100% tested.

3 For test conditions, see AC Test Conditions, Figures A, B.

4 These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage.

5 This parameter is guaranteed, but not tested.

6 WE is High for read cycle.

7 CE and OE are Low for read cycle.

8 Address valid prior to or coincident with CE transition Low.

9 All read cycle timings are referenced from the last valid address to the first transitioning address.

10 N/A

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 N/A

13 C=30pF, except on High Z and Low Z parameters, where C=5pF.

4/23/04; v.2.0

Alliance Semiconductor

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