APW7064 Просмотр технического описания (PDF) - Anpec Electronics
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APW7064 Datasheet PDF : 19 Pages
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APW7064
Operating Waveforms (Cont.)
Short Test
VCC=12V, VIN=12V
VOUT=3.3V, L=1uH
1
2
3
CH1: VOUT (2V/div)
CH2: UGATE (20V/div)
CH3: LGATE (10V/div)
Time: 2ms/div
Pin Description
PIN
NO.
NAME
FUNCTION
1
BOOT
A bootstrap circuit with a diode connected to VCC is used to create a voltage suitable to drive a logic-level
N-channel MOSFET.
2
UGATE
Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive for the high-side
MOSFET.
3
GND
The GND terminal provides return path for the IC bias current and the low-side MOSFET driver pull-low
current. Connect the pin to the system ground via very low impedance layout on PCBs.
4
LGATE
Connect this pin to the low-side N-channel MOSFET gate. This pin provides gate drive for the low-side
MOSFET.
Connect this pin to a 12V supply voltage. This pin provides bias supply for the control circuitry and the
5
VCC low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. It is
recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling.
This pin is the inverting input of the internal error amplifier. Connect this pin to the output (VOUT) of the
converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor
divider is determined using the following formula:
6
FB
VOUT
= 1.2 × 1+
ROUT
RGND
where ROUT is the resistor connected from VOUT to FB, and RGND is the resistor connected from FB to GND.
The FB pin is also monitored for under voltage events.
7
COMP
This pin is the output of PWM error amplifier. It is used to set the compensation components. In addition, if
the pin is pulled below 1.2V, it will disable the device.
8
PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source.
Copyright © ANPEC Electronics Corp.
8
Rev. A.3 - Aug., 2009
www.anpec.com.tw
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