AN5308 Просмотр технического описания (PDF) - Panasonic Corporation
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AN5308 Datasheet PDF : 25 Pages
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ICs for TV
AN5308NK
s Electrical Characteristics at Ta = 25°C (continued)
• Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min Typ Max Unit
Horizontal signal processing (continued)
F.B.P slice level (blanking)
F.B.P slice level (AFC1)
F.B.P delay time range
VFBP−1
VFBP−2
TH−FBP
H-center: typ. From HOUT rising
edge to FBP center
0.7 V
2.5 V
19 µs
B.G.P start position
From H. sync. rear edge to burst
gate pulse front edge
0.3 µs
Sandcastle pulse output temperature ∆V60(Ta)
characteristics
1.8 mV/deg
Sandcastle pulse input threshold
level temperature characteristics
∆V59(Ta)
0 mV/deg
F.B.P input threshold level
∆V61(Ta)
temperature characteristics (HBLK)
−1.8 mV/deg
F.B.P input threshold level
temperature characteristics (AFC1)
1 mV/deg
X-ray inside reference temperature
characteristics
Sandcastle pulse output vs. supply
voltage dependence (BGP)
Zener temperature characteristics: 0 mV/deg
+1.8 mV/deg
VCC2: 5 V ± 0.5 V
1 V/V
Sandcastle pulse output vs. supply
voltage (HBLK)
VCC2: 5 V ± 0.5 V
0.74 V/V
Sandcastle pulse output vs. supply
voltage (VBLK)
VCC2: 5 V ± 0.5 V
0.44 V/V
Hold down operation voltage
Vertical signal processing
Vertical BLK phase (wide)
VHTH VREF (= pin 6) = 6.2 V
2.71 2.81 2.91 V
PVBLK(W) Period from VBLK rising edge to 3.87 ms
vertical sync. falling edge
Vertical BLK phase (normal)
PVBLK Period from VBLK rising edge to 0.2 ms
vertical sync. falling edge
Neck break operation pin 60 voltage V60 Pin 6: 1.5 V
Vertical BLK pulse width (wide) TVBLK(W)
Y-signal processing
1.5 V
5.05 ms
Contrast variable range
AyG(CON)min Contrast: min.
Y-output amplitude VCC dependence ∆yG(VCC)
Y-output DC voltage VCC dependence ∆yG(VCC)
Y-noise level
VYNL
Delay line dynamic range
VDLmax
40 dB
0.4 dB/V
0.18 V/V
7 50 mV
0.7 V
9
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