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AN1816

USING THE HC912B32 TO IMPLEMENT THE DISTRIBUTED SYSTEMS INTERFACE (DSI) PROTOCOL

Freescale Semiconductor 

Application Note

Freescale Semiconductor, Inc.

Schematics and

Layout

Considerations -

Master Board

PP0/PW0

PS6/SCK

PS5/MOSI

PS4/MISO

PS7/SS

PS3

W18 R15

100Ω

PE1/IRQ

Vdd

C23

0.1µF

U9 - DSID

Vdd

DSI Ch.0 Rx Data

W17 - TP1

C24

0.1µF

1 SCLK

Vdd 16

2 CLK

DSI0F 15

3 DI

DSI0S 14

4 DO

DSI0R 13

5 CS

n.c. 12

6 RESET DSI1F 11

7 INT

DSI1S 10

8 Gnd DSI1R 9

U11 - DSIP

1 DSI0F

2 DSI0S

3 DSI0R

4 DSI1F

5 DSI1S

6 DSI1R

7 n.c.

8 CPCAP

Vdd 16

Gnd0 15

DSI0O 14

Vsup 13

DSI1O 12

Gnd1 11

n.c. 10

n.c. 9

1 W20

1 W22

W19 - TP2

DSI Ch.1 Rx Data

C22

0.1µF

W21

n.c.

25v

no pin +

Gnd

Bus Power

C26

10µF

Figure 10 Master Board Schematic

Figure 10 Master Board Schematic shows the schematic for the master

board. The board was based on an existing HC912B32 Evaluation

Board (EVB) with the addition of the required DSI circuitry. The

HC912B32 EVB circuitry allows the board to be used to evaluate

prototype hardware and software. When laying out the DSI circuitry on

the master board, the bus traces out of the MC33790 were made as wide

as possible to deal with the presence of the higher voltage (the DSI bus

maximum idle voltage is 25V). All components were positioned where

clock and bus trace lengths could be kept to a minimum. 0.1µF

capacitors were used to filter the bus supply voltage and to decouple the

power supplies to the MC68HC55 and MC33790. These capacitors were

placed as close to the ICs as possible.

AN1816

10

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