HM5225645FBP-B60 Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM5225645FBP-B60

256M LVTTL interface SDRAM 100 MHz 1-Mword × 64-bit × 4-bank/2-Mword × 32-bit × 4-bank PC/100 SDRAM

Hitachi -> Renesas Electronics 

HM5225645F-B60, HM5225325F-B60

Power-up Sequence and Initialization Sequence

Power up sequence

100 µs

VCC 0 V

CKE, DQMB Low

CLK Low

CS, DQ Low

Power stabilize

Initialization sequence

200 µs

Absolute Maximum Ratings

Parameter

Voltage on any pin relative to VSS

Supply voltage relative to VSS

Short circuit output current

Operating temperature

Storage temperature

Note: 1. Respect to VSS

Symbol

VT

VCC

Iout

Topr

Tstg

Value

–0.5 to VCC + 0.5

(≤ 4.6 (max))

–0.5 to +4.6

50

0 to +70 (Tj max = 110)

–55 to +125

Unit

V

V

mA

°C

°C

Note

1

1

DC Operating Conditions (Tcase = 0 to +70°C [Tj max = 110°C])

Parameter

Symbol

Min

Max

Supply voltage

VCC

3.0

3.6

VSS

0

0

Input high voltage

VIH

2.0

VCC + 0.3

Input low voltage

VIL

–0.3

0.8

Notes: 1. All voltage referred to VSS

2. The supply voltage with all VCC pins must be on the same level.

3. The supply voltage with all VSS pins must be on the same level.

4. VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.

5. VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS.

Unit

V

V

V

V

Notes

1, 2

3

1, 4

1, 5

8

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