UD61256DC08 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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UD61256DC08 Datasheet PDF : 13 Pages
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UD61256
Dynamic Characteristics
F ALL CYCLES
Symbol
3)
Alt.
IEC
Transition Time (Rise and Fall)
4)
tT
RAS Precharge Time
tRP
CAS Precharge Time
tCP
Row Address Set-up Time
tASR
Column Address Set-up Time
tASC
Row Address Hold Time
t RAH
Column Address Hold Time
tCAH
Column Address Hold Time ref. to RAS
tAR
Output Buffer Turn-off Delay
5)
tOFF
CAS to RAS Precharge Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period
F READ
tCRP
6)
tRAD
tRAL
tCLZ
tREF
tt
tw(RASH)
tw(CASH)
tsu(RA-RAS)
tsu(CA-CAS)
th(RAS-RA)
th(CAS-CA)
th(RAS-CA)
tv(CAS)
tCASH-RASL
tRAS-CA
tCA-RASH
tCASL-QX
trf
Random Read Cycle Time
12)
tRC
Access Time from RAS
7), 8)
tRAC
Access Time from Column Address 7), 8) tAA
Access Time from CAS
7), 8)
tCAC
RAS Pulse Width
tRAS
CAS Pulse Width
tCAS
Read Command Set-up Time
tRCS
Read Command Hold Time ref. to RAS 9) tRRH
Read Command Hold Time
9)
tRCH
RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
F WRITE
6)
tRCD
tCSH
tRSH
tcR
ta(RAS)
ta(CA)
ta(CAS)
tw(RASL)
tw(CASL)
tsu(R-CAS)
th(RAS-R)
th(CAS-R)
tRASL-CASL
tRASL-CASH
tCASL-RASH
Random Write Cycle Time
RAS Pulse Width
CAS Pulse Width
Write Command Pulse Width
Remarks: see page 7
12)
tRC
tRAS
tCAS
tWP
tcW
tw(RASL)
tw(CASL)
tw(W)
Min.
07
08
Max.
Unit
07
08
3
3
50
50 ns
50
60
ns
10
10
ns
0
0
ns
0
0
ns
10
10
ns
15
15
ns
55
60
ns
0
0
20
20 ns
5
5
ns
15
15
35
40 ns
35
40
ns
0
0
ns
4
4 ms
130
150
ns
70
80 ns
35
40 ns
20
20 ns
70
80 10000 10000 ns
20
20 10000 10000 ns
0
0
ns
0
0
ns
0
0
ns
20
20
50
60 ns
70
80
ns
20
20
ns
130
150
ns
70
80 10000 10000 ns
20
20 10000 10000 ns
15
15
ns
December 12, 1997
5
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