UD61256JC08 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG

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UD61256JC08

256K x 1 DRAM

Zentrum Mikroelektronik Dresden AG 

UD61256

Block Diagram

CAS

D

W

RAS

A0

A1

A2

A3

A4

A5

A6

A7

A8

Operation

Output Control

Data Input Amplifier

Write-Read Control

Clock Generator

Decoder

1 out of 4

A8X

A8Y

M

U

X

A0X to A7X

A0Y to A7Y

Function

RAS

CAS

Stand-by

Read

Write

H

X

L

L

L

L

Read- Write

FPM

Read

L

1st

cycle

L

2nd

cycle

L

L

H→L

H→L

FPM

Write

FPM

Read- Write

1st

cycle

L

2nd

cycle

L

1st

cycle

L

2nd

cycle

L

RAS only Refresh

L

H→L

H→L

H→L

H→L

H

HIDDEN Refresh*) Read L → H → L

L

Write L → H → L

L

*) Transfer of Refresh Address required

W

X

H

L

H→L

H

H

L

L

H→L

H→L

X

H

L

2

Data Output

Amplifier

Q

4 Write-Read

Amplifier

Data

Row

Decoder

Row

Decoder

VCC VSS

Address

R

C

Data

D

Q

X

X

X

Row

Column

X

High-Z

Output

Data

Row

Column Input Data High-Z

Row

Row

Column Input Data

Column

X

Output

Data

Output

Data

Column

X

Output

Data

Row

Column Input Data High-Z

Row

Row

Row

Row

Column Input Data

Column Input Data

Column Input Data

X

Column

X

Column Input Data

High-Z

Output

Data

Output

Data

High-Z

Output

Data

High-Z

December 12, 1997

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