CYM1841A Просмотр технического описания (PDF) - Cypress Semiconductor

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CYM1841A

256K x 32 Static RAM Module

Cypress Semiconductor 

CYM1841A

CYM1841C

Switching Waveforms

Read Cycle No. 1[8, 9]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2[8, 10]

DATA VALID

1841A–6

CS

tRC

OE

DATA OUT

tACS

tDOE

tLZOE

HIGH IMPEDANCE

tLZCS

DATA VALID

tHZOE

tHZCS

HIGH

IMPEDANCE

1841A–7

Write Cycle No. 1 (WE Controlled)[7]

ADDRESS

CS

WE

DATA IN

DATA OUT

tWC

tSCS

tAW

tHA

tSA

tPWE

DATA UNDEFINED

tSD

tHD

DATA VALID

tHZWE

tLZWE

HIGH IMPEDANCE

Notes:

8. WE is HIGH for read cycle.

9. Device is continuously selected, CS = VIL and OE= VIL.

10. Address valid prior to or coincident with CS transition LOW.

1841A–8

6

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