SCM6343YJ15AR Просмотр технического описания (PDF) - Motorola => Freescale
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SCM6343YJ15AR Datasheet PDF : 10 Pages
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WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3)
MCM6343–12
MCM6343–15
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
12
—
15
—
ns
4
Address Setup Time
Address Valid to End of Write
Address Valid to End of Write (G High)
tAVBL
0
—
0
—
ns
tAVBH
10
—
12
—
ns
tAVBH
9
—
10
—
ns
Byte Pulse Width
tBLWH
10
—
12
—
ns
tBLEH
Byte Pulse Width (G High)
tBLWH
9
tBLEH
—
10
—
ns
Data Valid to End of Write
tDVBH
6
—
7
—
ns
Data Hold Time
tBHDX
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
A (ADDRESS)
E (CHIP ENABLE)
LB, UB (BYTE ENABLE)
W (WRITE ENABLE)
D (DATA IN)
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
tAVAV
tAVBH
tAVBL
tBLEH
tBLWH
tDVBH
DATA VALID
tBHDX
Q (DATA OUT)
HIGH–Z
HIGH–Z
MCM6343
8
MOTOROLA FAST SRAM
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