AK4552 Просмотр технического описания (PDF) - Asahi Kasei Microdevices

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AK4552

3V 96kHz 24Bit ∆Σ CODEC

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4552]

„ Power-down & Reset

The ADC and DAC of AK4552 are placed in the power-down mode by bringing power down pin, PDN = “L” and each

digital filter is also reset at the same time. These resets should always be done after power-up. In case of the ADC, an anlog

initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after

2081 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 6 shows the power-up

sequence.

PDN

ADC Internal

State

DAC Internal

State

ADC In

(Analog)

ADC Out

(Digital)

DAC In

(Digital)

DAC Out

(Analog)

Clock In

MCLK,LRCK,BCLK

External

Mute

Normal Operation

Normal Operation

GD

Power-down

Power-down

2081/fs

Init Cycle

Normal Operation

Normal Operation

GD

Idle Noise

GD

(1)

“0”data

“0”data

(1)

Idle Noise

GD

The clocks may be stopped.

Mute ON

Figure 6. Power-up Sequence

(1) Click noise occurs at the “↑↓” of PDN signal. Please mute the analog output external if the click noise influences

system application.

MS0055-E-01

- 11 -

2001/02

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