AK4525 Просмотр технического описания (PDF) - Asahi Kasei Microdevices
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AK4525 Datasheet PDF : 18 Pages
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ASAHI KASEI
[AK4525]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.5 ∼ 5.5V; VD=3.1 ∼ 5.5V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
256fs
8.192
384fs
12.288
512fs
16.384
MCKO Output
Frequency
fMCK
8.192
Duty Cycle
dMCK
50
Rise Time
(Note 15)
tR
Fall time
(Note 15)
tF
LRCK Timing
Frequency
fs
32
Duty Cycle
dfs
45
Serial Interface Timing
Slave mode
SCLK Period
tSCK
320
SCLK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to SCLK “↑” (Note 16)
tLRS
45
SCLK “↑” to LRCK Edge (Note 16)
tSLR
45
LRCK to SDTO (MSB)
tLRM
SCLK “↓” to SDTO
tSSD
SDTI Hold Time
tSDH
40
SDTI Setup Time
tSDS
25
Master mode
SCLK Frequency
fSCK
64fs
SCLK Duty
dSCK
50
SCLK “↓” to LRCK
SCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tMSLR
-20
tSSD
tSDH
40
tSDS
25
Reset Timing
PDN Pulse Width
(Note 17)
tPD
150
PDN “↑” to SDTO valid
(Note 18)
tPDV
516
max
12.288
18.432
24.576
24.576
5
5
48
55
Units
MHz
MHz
MHz
MHz
%
ns
ns
kHz
%
ns
ns
ns
ns
ns
40
ns
70
ns
ns
ns
Hz
%
20
ns
70
ns
ns
ns
ns
1/fs
Notes: 15. VD=3.1V, 0.8 ∼ 2.0V.
16. SCLK rising edge must not occur at the same time as LRCK edge.
17. The AK4525 can be reset by bringing PDN “L”. When the state of CMODE changes during operation, the
AK4525 should be reset by PDN. PDN should be held “L” for 5ms to allow the X’tal oscillation to begin at
power-up.
18. These cycles are the number of LRCK rising from PDN rising.
MS0053-E-00
-7-
2000/9
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