AI5412 Просмотр технического описания (PDF) - A1 PROs co., Ltd.
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AI5412 Datasheet PDF : 20 Pages
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Ai5412
External Synchronization
1) External/internal sync selection
External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL
and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations.
Input
pattern
EXT pin
output
Sync state
VR/SYNC pin : SYNC signal VR/SYNC pin : VD signal
HPLL pin : Open
HPLL pin : HD signal
ESYNC pin : Open
ESYNC pin : VDD
High
High
External sync
External sync
VR/SYNC pin : Open
HPLL pin : Open
ESYNC pin : Open
Low
Internal sync
Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal.
The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as
the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator
for improving the oscillation accuracy for internal synchronization.
2) Modes for external synchronization
Mode
Field accumulation
Frame accumulation
SYNC
synchronization
Interlace
Non-interlace
O
X
(Cannot be accomplished since
interlace operation is the prior condition)
O
X
(Cannot be accomplished since
interlace operation is the prior condition)
Interlace
O
VD/HD
synchronization Non-interlace
O
O
X
(Not practically applicable since
the sensitivity is halved)
3) Reset operation
SYNC synchronization
The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset is
performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse. For
CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these
reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard.
VD/HD synchronization
V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse supplied
externally. Therefore, this enables V reset operation regardless of the field line number. The phase
difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit identifies
whether the field is odd or even.
(VDR must have a pulse width of 2H or more.)
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