EVAL-ADV7441AFEZ_2 Просмотр технического описания (PDF) - Analog Devices

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EVAL-ADV7441AFEZ_2

10-Bit Integrated, Multiformat SDTV/HDTV Video Decoder, RGB Graphics Digitizer, and 2:1 Multiplexed HDMI/DVI Interface

Analog Devices 

TIMING DIAGRAMS

t3

xDA

t5

t3

t6

t1

xCL

t2

t7

t4

t8

NOTES

1. THE PREFIX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S.

Figure 2. I2C Timing

LLC

t9

t10

P0 TO P29, VS,

HS, DE/FIELD,

SFL/SYNC_OUT

t11

t12

Figure 3. Pixel Port and Control SDR Output Timing (SDP Core)

t9

t10

LLC

P0 TO P29, VS,

HS, DE/FIELD

t13

t14

Figure 4. Pixel Port and Control SDR Output Timing (CP Core)

SCLK

LRCLK

I2Sx

LEFT-JUSTIFIED

MODE

I2Sx

I2S MODE

I2Sx

RIGHT-JUSTIFIED

MODE

t15

t16

t17

t18

t19

MSB

MSB – 1

t20

t19

MSB

MSB – 1

t20

MSB

NOTES

1. THE SUFFIX x REFERS TO PIN NAMES ENDING WITH 0, 1, 2, AND 3.

Figure 5. I2S Timing

Rev. B | Page 9 of 28

t19

t20

LSB

ADV7441A

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