ADV7441A Просмотр технического описания (PDF) - Analog Devices
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ADV7441A Datasheet PDF : 28 Pages
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ADV7441A
Pin No.
107
76 to 81, 93 to 96,
98, 99
24 to 33, 36 to 47,
52 to 55, 58 to 61
19
Mnemonic
TEST4
AIN1 to AIN12
P0 to P29
INT1
20
SFL/SYNC_OUT/INT2
17
HS/CS
18
VS/FIELD
16
DE/FIELD
11
SDA
12
SCL
13
ALSB
21
RESET
51
LLC
65
XTAL1
66
XTAL
70
ELPF
102
AUDIO_ELPF
85
REFOUT
86
CML
90
REFN
92
REFP
63
HS_IN/CS_IN
62
VS_IN
75
SOG
97
SOY
112
RXA_CN
113
RXA_CP
115
RXA_0N
116
RXA_0P
118
RXA_1N
119
RXA_1P
121
RXA_2N
122
RXA_2P
Type 1
I/O
I
Description
Test Pin. Do not connect.
Analog Video Input Channels.
O
Video Pixel Output Port.
O
Interrupt Signal. Can be active low or active high. The set of events that triggers an
interrupt is under user control.
O
Subcarrier Frequency Lock (SFL). Contains a serial output stream that can be used to
lock the subcarrier frequency when this decoder is connected to any Analog Devices
digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available only in CP mode.
Interrupt Signal (INT2).
O
Horizontal Synchronization Output Signal (HS). Output by the SDP and CP.
Composite Synchronization (CS). A single signal containing both horizontal and
vertical synchronization pulses.
O
Vertical Synchronization Output Signal (VS). Output by the SDP and CP.
Field Synchronization Output Signal (FIELD). Field synchronization output signal in all
interlaced video modes.
O
Data Enable Signal (DE). Indicates active pixel data.
Field Synchronization Output Signal (FIELD). Field synchronization output signal in all
interlaced video modes.
I/O
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
I
I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for
the control port.
I
This pin sets the second LSB of the slave address for each ADV7441A register map.
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7441A circuitry.
O
Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz.
O
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an
external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In
crystal mode, the crystal must be a fundamental crystal.
I
Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V
28.63636 MHz clock oscillator source to clock the ADV7441A.
O
The recommended external loop filter must be connected to this ELPF pin.
O
The recommended external loop filter must be connected to this AUDIO_ELPF pin.
O
Internal Voltage Reference Output.
O
Common-Mode Level for the Internal ADCs.
O
Internal Voltage Reference Output.
O
Internal Voltage Reference Output.
I
HS Input Signal. Used in analog mode for 5-wire timing mode.
CS Input Signal. Used in analog mode for 4-wire timing mode.
For optimal performance, a 100 Ω series resistor is recommended on the
HS_IN/CS_IN pin.
I
VS Input Signal. Used in analog mode for 5-wire timing mode. For optimal performance,
a 100 Ω series resistor is recommended on the VS_IN pin.
I
Synchronization-on-Green Input. This pin is used in embedded synchronization mode.
I
Synchronization-on-Luma Input. This pin is used in embedded synchronization mode.
I
Digital Input Clock Complement of Port A in the HDMI Interface.
I
Digital Input Clock True of Port A in the HDMI Interface.
I
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
I
Digital Input Channel 0 True of Port A in the HDMI Interface.
I
Digital Input Channel 1 Complement of Port A in the HDMI Interface.
I
Digital Input Channel 1 True of Port A in the HDMI Interface.
I
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
I
Digital Input Channel 2 True of Port A in the HDMI Interface.
Rev. B | Page 12 of 28
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