ADP3212AMNR2G Просмотр технического описания (PDF) - ON Semiconductor

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ADP3212AMNR2G

7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller

ON Semiconductor 

ADP3212A, NCP3218A

PIN ASSIGNMENT

Pin No. Mnemonic

11

TTSNS

12

GND

13

IREF

14

RPM

15

RT

16

RAMP

17

LLINE

18

CSREF

19

CSSUM

20

CSCOMP

21

ILIM

22

OD3

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 to

48

PWM3

SWFB3

BST2

DRVH2

SW2

SWFB2

DRVL2

PGND

DRVL1

PVCC

SWFB1

SW1

DRVH1

BST1

VCC

PH1

PH0

DPRSLP

PSI

VID6 to VID0

Description

Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected

to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this

pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling

function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.

Analog and Digital Signal Ground.

This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground.

RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on

threshold voltage.

Multi−phase Frequency Setting Input. An external resistor connected between this pin and GND sets the

oscillator frequency of the device when operating in multi−phase PWM mode threshold of the converter.

PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets

the slope of the internal PWM stabilizing ramp used for phase−current balancing.

Output Load Line Programming Input. The center point of a resistor divider between CSREF and

CSCOMP is connected to this pin to set the load line slope.

Current Sense Reference Input. This pin must be connected to the common point of the output inductors.

The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop

transient control of the converter output voltage.

Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor

currents to provide total current information.

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of

the current−sense amplifier and the positioning loop response time.

Current Limit Setpoint. An external resistor from this pin to CSCOMP sets the current limit threshold of the

converter.

Multi−phase Output Disable Logic Output. This pin is actively pulled low when the APD3212A/NCP3218A

enters single−phase mode or during shutdown. Connect this pin to the SD inputs of the Phase−3 MOSFET

drivers.

Logic−Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the

ADP3611.

Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should be left

open for 1 or 2 phase configuration.

High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage

while the high−side MOSFET is on.

High−Side Gate Drive Output for Phase 2.

Current Return for High−Side Gate Drive for phase 2.

Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should be left

open for 1 phase configuration.

Low−Side Gate Drive Output for Phase 2.

Low−Side Driver Power Ground

Low−Side Gate Drive Output for Phase 1.

Power Supply Input/Output of Low−Side Gate Drivers.

Current Balance Input for phase 1. Input for measuring the current level in phase 1.

Current Return For High−Side Gate Drive for phase 1.

High−Side Gate Drive Output for Phase 1.

High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage

while the high−side MOSFET is on.

Power Supply Input/Output of the Controller.

Phase Number Configuration Input. Connect to VCC for 3 phase configuration.

Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for

multi−phase configuration.

Deeper Sleep Control Input.

Power State Indicator Input. Pulling this pin to GND forces the APD3212A/NCP3218A to operate in

single−phase mode.

Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB

regulation voltage from 0.3 V to 1.5 V (see Table 3).

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