ADM2483BRW Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADM2483BRW

Half-Duplex, iCoupler® Isolated RS-485 Transceiver

Analog Devices 

Data Sheet

APPLICATIONS INFORMATION

POWER_VALID INPUT

To avoid chatter on the A and B outputs caused by slow power-

up and power-down transients on VDD1 (>100 μs/V), the

ADM2483 features a power_valid (PV) digital input. This pin

should be driven low until VDD1 exceeds 2.0 V. When VDD1 is

greater than 2.0 V, the pin should be driven high. Conversely,

upon power-down, the PV should be driven low before VDD1

reaches 2.0 V.

The power_valid input can be driven, for example, by the

output of a system reset circuit such as the ADM809Z, which

has a threshold voltage of 2.32 V.

VDD1

ADM809Z RESET

VDD1

ADM2483

PV

GND1

VDD1 2.0V

2.32V

2.32V 2.0V

RESET

tPOR

Figure 29. Driving PV with ADM809Z

ADM2483

ISOLATED POWER SUPPLY CIRCUIT

The ADM2483 requires isolated power capable of 5 V at

100 mA to be supplied between the VDD2 and GND2 pins. If no

suitable integrated power supply is available, a discrete circuit,

such as the one in Figure 30, can be used. A center-tapped

transformer provides electrical isolation. The primary winding

is excited with a pair of square waveforms that are 180° out of

phase with each other. A pair of Schottky diodes and a

smoothing capacitor are used to create a rectified signal from

the secondary winding. The ADP667 linear voltage regulator

provides a regulated power supply to the ADM2483’s bus-side

circuitry.

To create the pair of square waves, a D-type flip-flop with

complementary Q/Q outputs is used. The flip-flop can be

connected so that output Q follows the clock input signal. If no

local clock signal is available, a simple digital oscillator can be

implemented with a hex-inverting Schmitt trigger and a resistor

and capacitor. In this case, values of 3.9 kΩ and 1 nF generate a

364 kHz square wave. A pair of discrete NMOS transistors,

switched by the Q/Q flip-flop outputs, conduct current through

the center tap of the primary transformer, winding in an

alternating fashion.

3.9k

VCC

100nF

VCC 100nF

PR CLR

D

Q

ISOLATION

BARRIER

BS107A

SD103C

VCC

5V

IN

OUT

22F

ADP667

74HC74A

CLK

BS107A

Q

SET GND SHDN

74HC14

1nF

78253

SD103C

VCC

VDD1

VDD2

ADM2483

GND1

GND2

Figure 30. Isolated Power Supply Circuit

Rev. C | Page 17 of 20

Share Link: