ADM1029ARQZ-R7 Просмотр технического описания (PDF) - ON Semiconductor
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ADM1029ARQZ-R7
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ADM1029ARQZ-R7 Datasheet PDF : 50 Pages
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3 MSBs
of ADC
111
110
101
100
011
010
001
000
Table I. Resistor Ratios for Setting Serial Bus Address
Ideal Ratio
R2/(R1 + R2)
N/A
0.8125
0.6875
0.5625
0.4375
0.3125
0.1875
N/A
R1
(k⍀)
0
18
22
12
15
47
82
∞
R2
(k⍀)
∞
82
47
15
12
22
18
0
Actual
R2/(R1 + R2)
1
0.82
0.6812
0.5556
0.4444
0.3188
0.18
0
ADM1029
Error
%
0
+0.75
–0.63
–0.69
+0.69
+0.63
–0.75
0
Address
0101111
0101110
0101101
0101100
0101011
0101010
0101001
0101000
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus an R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1 the master will read from the
slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop condi-
tions are established. In WRITE mode, the master will pull
the data line high during the tenth clock pulse to assert a
STOP condition. In READ mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, high during the tenth clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
Rev. 1 | Page 8 of 50 | www.onsemi.com
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