ADM1067ACPZ(RevE) Просмотр технического описания (PDF) - Analog Devices

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ADM1067ACPZ
(Rev.:RevE)

Super Sequencer with Open-Loop Margining DACs

Analog Devices 

Data Sheet

Parameter

SERIAL BUS TIMING3

Clock Frequency, fSCLK

Bus Free Time, tBUF

Start Setup Time, tSU;STA

Stop Setup Time, tSU;STO

Start Hold Time, tHD;STA

SCL Low Time, tLOW

SCL High Time, tHIGH

SCL, SDA Rise Time, tR

SCL, SDA Fall Time, tF

Data Setup Time, tSU;DAT

Data Hold Time, tHD;DAT

Input Low Current, IIL

SEQUENCING ENGINE TIMING

State Change Time

Min Typ

1.3

0.6

0.6

0.6

1.3

0.6

100

5

10

Max Unit Test Conditions/Comments

400 kHz

μs

μs

μs

μs

μs

μs

300 ns

300 ns

ns

ns

1

μA VIN = 0 V

μs

1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2 Specification is not production tested but is supported by characterization data at initial product release.

3 Timing specifications are guaranteed by design and supported by characterization data.

ADM1067

Rev. E | Page 7 of 31

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