ADL5570(RevPrG) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
Список матч
ADL5570 Datasheet PDF : 10 Pages
| |||
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5570
VCC1 5
RFIN 6
GND 7
VREG 8
PIN 1
INDICATOR
ADL5570
TOP VIEW
(Not to Scale)
16 NC
15 RFOUT
14 RFOUT
13 NC
Figure 2. ADL5570 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
5
VCC1
Connect to Power Supply.
6
RFIN
Matched RF Input.
8
VREG
When VREG is low, the device goes into sleep mode, reducing supply current to 1 uA. When VREG is
high (2.85 V), the device operates in its normal transmit mode. When high, VREG draws a bias current of
approximately 10 mA.
9
CFLT
A Ground Referenced Capacitor. It should be connected to this node to reduce bias line noise (see
figure 8).
10
MODE
Switches Between High Power and Low Power Modes. When MODE is low (0 V), the device operates in
high power mode. When MODE is high (2.5 V), the device operates in low power mode.
14, 15
RFOUT
Unmatched RF Output. These parallel outputs can be matched to 50 Ω using strip-line and shunt
capacitance. The power supply voltage should be connected to these pins through a choke inductor.
2
VCC2
This power supply pin should be connected to the supply via a choke circuit (see Figure 8).
4
STBY
When STBY is low (0 V), the device operates in transmit mode. When the radio is receiving data, STBY
can be taken high (2.5 V), reducing supply current to 10 mA.
1, 11 to 13, 16 N/C
No Connect. Do not connect these pins.
7
GND
Connected to Ground.
Exposed
Paddle
The exposed paddle should be soldered down to a low impedance ground plane (use multiple vias (at
least 9) to stitch together the ground planes) for optimum electrical and thermal performance.
Table 4. Operating Modes1
Mnemonic
Normal Operation
VREG
High
MODE
Low
STBY
Low
Low Power Mode, POUT ≤ 10dBm
High
High
Low
Standby Mode
High
X
High
Sleep Mode
Low
X
X
1 X = don’t care.
Rev. PrG | Page 5 of 10
Share Link: 