ADL5336ACPZ-R7 Просмотр технического описания (PDF) - Analog Devices

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ADL5336ACPZ-R7

Cascadable IF VGAs with Programmable RMS Detectors

Analog Devices 

Data Sheet

TIMING DIAGRAMS

CLK

LE

DATA

tLS

tDS tDH

WRITE BIT

tCLK

tPW

LSB

LSB + 1

LSB + 2

LSB + 3

MSB – 3

MSB – 2

MSB – 1

tLH

MSB

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A WRITE

OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 8-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING

EDGES OF THE CLOCK.

Figure 2. Write Mode Timing Diagram

ADL5336

tD

tCLK

tPW

CLK

tLH

tLS

LE

tDS tDH

DATA

READ BIT

DC

DC

DC

DC

DC

DC

DC

DC

SDO

LSB

LSB + 1

LSB + 2

LSB + 3

MSB – 3

MSB – 2

MSB – 1

MSB

NOTES

1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 8-BIT REGISTER. FOR A READ

OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE 8-BIT WORD IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES

OF THE CLOCK.

Figure 3. Read Mode Timing Diagram

Rev. C | Page 5 of 30

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