ADG738 Просмотр технического описания (PDF) - Analog Devices
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ADG738 Datasheet PDF : 20 Pages
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ADG738/ADG739
8051 INTERFACE TO ADG738/ADG739
A serial interface between the ADG738/ADG739 and the 8051
is shown in Figure 28. TXD of the 8051 drives SCLK of the
ADG738/ADG739, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
drive SYNC.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user has to ensure that the data in the SBUF
register is arranged correctly as the switch expects MSB first.
When data is to be transmitted to the matrix switch, P3.3 is
taken low. Data on RXD is clocked out of the microcontroller
on the rising edge of TXD and is valid on the falling edge. As a
result no glue logic is required between the ADG738/ADG739
and microcontroller interface.
P3.3
80C51/80L51*
RXD
TXD
SYNC
DIN ADG738/
ADG739
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 28. 8051 Interface to ADG738/ADG739
Data Sheet
MC68HC11 INTERFACE TO ADG738/ADG739
Figure 29 shows an example of a serial interface between the
ADG738/ADG739 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the matrix switch, while the
MOSI output drives the serial data line, DIN. SYNC is driven
from one of the port lines, in this case PC7.
PC7
MC68HC11* MOSI
SCK
SYNC
ADG738/
DIN ADG739
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. MC68HC11 Interface to ADG738/ADG739
The 68HC11 is configured for master mode; MSTR = 1, CPOL
= 0, and CPHA = 1. When data is transferred to the part, PC7 is
taken low, data is transmitted MSB first. Data appearing on the
MOSI output is valid on the falling edge of SCK.
If the user wishes to verify the data previously written to the
input shift register, the DOUT line could be connected to MISO
of the MC68HC11, and with SYNC low, the input shift register
would clock data out on the rising edges of SCLK.
Rev. A | Page 16 of 20
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