EV-ADF4157SD1Z Просмотр технического описания (PDF) - Analog Devices
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EV-ADF4157SD1Z Datasheet PDF : 24 Pages
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Data Sheet
ADF4157
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD
Low Power Sleep Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH)4
Normalized 1/f Noise (PN1_f)5
Phase Noise Floor6
Phase Noise Performance7
5800 MHz Output8
B Version1
0.5/6.0
10/300
0.4/AVDD
0.7/AVDD
10
±100
32
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
VDD – 0.4
0.4
2.7/3.3
AVDD
AVDD/5.5
29
10
−211
−110
−137
−133
−87
Unit
GHz min/max
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
V min
V max
V min/max
V min/V max
mA max
µA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Test Conditions/Comments
−10 dBm/0 dBm min/max; for lower frequencies, ensure slew rate
(SR) > 400 V/µs
For fREFIN < 10 MHz, ensure slew rate > 50 V/µs
For 10 MHz < fREFIN < 250 MHz, biased at AVDD/22
For 250 MHz < fREFIN < 300 MHz, biased at AVDD/22
Programmable
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
Sink and source current
0.5 V < VCP < VP – 0.5
0.5 V < VCP < VP – 0.5
VCP = VP/2
Open-drain 1 kΩ pull-up to 1.8 V
CMOS output chosen
IOL = 500 µA
23 mA typical
PLL loop B/W = 500 kHz;
measured at 100 kHz
10 kHz offset; normalized to 1 GHz
@ 10 MHz PFD frequency
@ 25 MHz PFD frequency
@ VCO output
@ 2 kHz offset, 25 MHz PFD frequency
1 Operating temperature of B version is −40°C to +85°C.
2 AC-coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N).
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
7 The phase noise is measured with the EV-ADF4157SD1Z and the Agilent E5052A phase noise system.
8 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 2 kHz; RFOUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
Rev. D | Page 3 of 24
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