VDD8608A8A-75BA Просмотр технического описания (PDF) - A-Data Technology
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VDD8608A8A-75BA Datasheet PDF : 9 Pages
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A-Data
ADD8616A8A
AC Characteristics
Parameter
Symbol
-75BA
Min
Max
System clock /CAS Latency = 2.5 tCK2.5
7.5
12
Cycle time /CAS Latency = 2
tCK2
7.5
12
Clock high pulse width
tCHW
0.45 0.55
Clock low pulse width
tCLW
0.45 0.55
Access time form CK to /CK
tAC
-0.75 0.75
Data strobe edge to clock edge
tDQSCK -0.75 0.75
Clock to first rising edge of DQS delay tDQSS 0.75 1.25
/RAS cycle time
tRC
65
-
/RAS to /CAS delay
tRCD
20
-
/RAS active time
tRAS
45
120K
/RAS precharge time
tRP
20
-
/RAS to /RAS bank active delay
tRRD
15
-
/CAS to /CAS delay
tCCD
1
-
Data-in setup time (to DQS)
tDS
0.5
-
Data-in hold time (to DQS)
tDH
0.5
-
DQS Falling Edge to CLK Setup Time tDSS
0.2
-
DQS Falling Edge Hold Time from CLK tDSH
0.2
-
Input setup time
tIS
0.9
-
Input hold time
tIH
0.9
-
DQS-in high level width
tDSH
0.35
-
DQS-in low level width
tDSL
0.35
-
Clock to DQS write preamble setup time tWPRES 0
-
Write preamble
tWPST
0.4
06
Data strobe edge to output data edge tDQSQ
0.5
Mode register set cycle time
tMRD
15
DQS read preamble
tRPRE
0.9
1.1
-75B
Unit
Min Max
7.5
12
10
12
ns
0.45 0.55 CLK
0.45 0.55 CLK
-0.75 0.75 ns
-0.75 0.75 ns
0.75 1.25 CLK
65
-
ns
20
-
ns
45 120K ns
20
-
ns
15
-
ns
1
- CLK
0.5
-
ns
0.5
-
ns
0.2
- CLK
0.2
- CLK
0.9
-
ns
0.9
-
ns
0.35
- CLK
0.35
- CLK
0
-
ns
0.4
06 CLK
0.5 ns
15
0.9 1.1 CLK
Rev 2 April, 2002
7
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