AD9868 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
Список матч
AD9868 Datasheet PDF : 36 Pages
| |||
AD9868
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 6.
Parameter
READ OPERATION2 (See Figure 9)
Output Data Rate
Three-State Output Enable Time (tPZL)
Three-State Output Disable Time (tPLZ)
Rx Data Valid Time (tVT)
Rx Data Output Delay (tOD)
WRITE OPERATION (See Figure 8)
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (tDS)
Tx Data Hold Time (tDH)
Latch Enable Time (tEN)
Latch Disable Time (tDIS)
1 See the Explanation of Test Levels section.
2 CLOAD = 5 pF for digital data outputs.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level1
II
II
II
II
II
II
II
II
II
II
II
Min
Typ
Max
Unit
20
80
MSPS
3
ns
3
ns
1.5
ns
4
ns
40
80
MSPS
20
50
MSPS
1
ns
2.5
ns
3
ns
3
ns
FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 7.
Parameter
Tx PATH INTERFACE (See Figure 12)
Input Nibble Rate (2× Interpolation)
Input Nibble Rate (4× Interpolation)
Tx Data Setup Time (tDS)
Tx Data Hold Time (tDH)
Rx PATH INTERFACE2 (See Figure 13)
Output Nibble Rate
Rx Data Valid Time (tDV)
Rx Data Hold Time (tDH)
1 See the Explanation of Test Levels section.
2 CLOAD = 5 pF for digital data outputs.
Temp
Full
Full
Full
Full
Full
Full
Full
Test Level1
II
II
II
II
II
II
II
Min
Typ
Max
Unit
80
160
MSPS
40
100
MSPS
2.5
ns
1.5
ns
40
160
MSPS
3
ns
0
ns
Rev. 0 | Page 8 of 36
Share Link: 