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AD977ABRS

16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter

Analog Devices 

AD977/AD977A

CONVERSION CONTROL

The AD977/AD977A is controlled by two signals: R/C and CS.

When R/C is brought low, with CS low, for a minimum of 50 ns,

the input signal will be held on the internal capacitor array and

a conversion “n” will begin. Once the conversion process does

begin, the BUSY signal will go low until the conversion is com-

plete. Internally, the signals R/C and CS are OR’d together and

there is no requirement on which signal is taken low first when

initiating a conversion. The only requirement is that there be at

least 10 ns of delay between the two signals being taken low.

After the conversion is complete the BUSY signal will return

high and the AD977/AD977A will again resume tracking the

input signal. Under certain conditions the CS pin can be tied

Low and R/C will be used to determine whether you are initiat-

ing a conversion or reading data. On the first conversion, after

the AD977/AD977A is powered up, the DATA output will be

indeterminate.

Conversion results can be clocked serially out of the AD977/

AD977A using either an internal clock, generated by the

AD977/AD977A, or by using an external clock. The AD977/

AD977A is configured for the internal data clock mode by pull-

ing the EXT/INT pin low. It is configured for the external clock

mode by pulling the EXT/INT pin high.

INTERNAL DATA CLOCK MODE

The AD977/AD977A is configured to generate and provide the

data clock when the EXT/INT pin is held low. Typically CS will

be tied low and R/C will be used to initiate a conversion “n.”

During the conversion the AD977/AD977A will output 16 bits of

data, MSB first, from conversion “n-1” on the DATA pin. This

data will be synchronized with 16 clock pulses provided on the

DATACLK pin. The output data will be valid on both the

rising and falling edge of the data clock as shown in Figure 3.

After the LSB has been presented, the DATA pin will assume

whatever state the TAG input was at during the start of con-

version, and the DATACLK pin will stay low until another

conversion is initiated.

EXTERNAL DATA CLOCK MODE

The AD977/AD977A is configured to accept an externally sup-

plied data clock when the EXT/INT pin is held high. This mode

of operation provides several methods by which conversion

results can be read from the AD977/AD977A. The output data

from conversion “n-1” can be read during conversion “n,” or the

output data from conversion “n” can be read after the conver-

sion is complete. The external clock can be either a continuous

or discontinuous clock. A discontinuous clock can be either

CS, R/C

BUSY

MODE

ACQUIRE

t1

t3

t2

t5

CONVERT

t6

t4

ACQUIRE

t7

Figure 2. Basic Conversion Timing

CONVERT

R/C

DATACLK

DATA

BUSY

t8

t1

t2

t9

1

2

3

t10

t11

MSB VALID

BIT 14

VALID

BIT 13

VALID

t6

15

16

BIT 1

VALID

LSB VALID

Figure 3. Serial Data Timing for Reading Previous Conversion Results with Internal Clock (CS, EXT/ INT and TAG Set to

Logic Low)

–8–

REV. D

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