AD9726 Просмотр технического описания (PDF) - Analog Devices

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AD9726

16-Bit, 400 MSPS Digital-to-Analog Converter

Analog Devices 

AD9726

Parameter

SERIAL PORT INTERFACE

SCLK Frequency (fSCLK)

SCLK Rise/Fall Time

SCLK Pulse Width High (tCPWH)

SCLK Pulse Width Low (tCPWL)

SCLK Setup Time (tCSU)

SDIO Setup Time (tDSU)

SDIO Hold Time (tDH)

SDIO/SDO Valid Time (tDV)

RESET PULSE WIDTH

TIMING DIAGRAMS

DAC CLOCK

DATACLOCK OUTPUT

Min

Typ

30

30

30

30

0

1.5

tDCPD-DDR

DATA BUS

DATACLOCK INPUT

tDSU-DDR

Figure 2. DDR Timing Diagram

DAC CLOCK

DATACLOCK OUTPUT

tDCPD-SDR

tDH-DDR

DATA BUS

DATACLOCK INPUT

tDSU-SDR

Figure 3. SDR Timing Diagram

tDH-SDR

DB0 TO DB15

CLK+/CLK–

tDSU-BYPASS

tDH-BYPASS

IOUTA OR IOUTB

tPD-BYPASS

Figure 4. Data Synchronization Bypass Timing Diagram

Max

Unit

15

MHz

1

ms

ns

ns

ns

ns

ns

30

ns

ns

Rev. B | Page 6 of 24

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