AD9726BSV Просмотр технического описания (PDF) - Analog Devices
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AD9726BSV Datasheet PDF : 16 Pages
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Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CLKVDD 1
REXT 2
CLKVDD 3
CLKGND 4
CLK+ 5
CLK– 6
CLKGND 7
DGND 8
DVDD 9
DB15+ 10
DB15– 11
DB14+ 12
DB14– 13
DB13+ 14
DB13– 15
DB12+ 16
DB12– 17
DB11+ 18
DB11– 19
DBVDD 20
PIN 1
IDENTIFIER
AD9726
TOP VIEW
(Not to Scale)
60 FSADJ
59 REFIO
58 RESET
57 CSB
56 SCLK/SYNC_UPD
55 SDIO
54 SDO/SYNC_ALRM
53 DGND
52 DVDD
51 DB0–
50 DB0+
49 DB1–
48 DB1+
47 DB2–
46 DB2+
45 DB3–
44 DB3+
43 DB4–
42 DB4+
41 DBGND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AD9726
Figure 4. Pin Configuration
Table 4. Pin Function Description
Pin Name
No.
Description
Pin Name
No.
1
CLKVDD
Clock Supply Voltage
41 DBGND
2
REXT
Bias Resistor. Sets DATACLK_OUT drive
strength. Nominally 1 kΩ to DBGND
42 DB4+
3
CLKVDD
Clock Supply Voltage
43 DB4–
4
CLKGND
Clock Supply Common
44 DB3+
5
CLK+
Clock Input–True
45 DB3–
6
CLK–
Clock Input–Complement
46 DB2+
7
CLKGND
Clock Supply Common
47 DB2–
8
DGND
Digital Common
48 DB1+
9
DVDD
Digital Supply Voltage
49 DB1–
10 DB15+
Digital Input Bit 15–True
50 DB0+
11 DB15–
Digital Input Bit 15–Complement
51 DB0–
12 DB14+
Digital Input Bit 14–True
52 DVDD
13 DB14–
Digital Input Bit 14–Complement
53 DGND
14 DB13+
Digital Input Bit 13–True
54 SDO/SYNC_ALRM
15 DB13–
16 DB12+
Digital Input Bit 13–Complement
Digital Input Bit 12–True
55 SDIO
56 SCLK/SYNC_UPD
17 DB12–
18 DB11+
19 DB11–
20 DBVDD
Digital Input Bit 12–Complement
Digital Input Bit 11–True
Digital Input Bit 11–Complement
Digital Data Supply Voltage
57 CSB
58 RESET
59 REFIO
60 FSADJ
Description
Digital Data Supply Common
Digital Input Bit 4–True
Digital Input Bit 4–Complement
Digital Input Bit 3–True
Digital Input Bit 3–Complement
Digital Input Bit 2–True
Digital Input Bit 2–Complement
Digital Input Bit 1–True
Digital Input Bit 1–Complement
Digital Input Bit 0–True
Digital Input Bit 0–Complement
Digital Supply Voltage
Digital Common
SPI_DIS = 1: Data/Clock
Synchronization Alarm
SPI Serial Data Input/Output
SPI_DIS = 1: Data/Clock
Synchronization Update Required
SPI Chip Select (Active Low)
Hardware Reset
Reference Output, 1.2 V Nominal
Full-Scale Current Adjust
Rev. PrD | Page 7 of 16
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