AD9725 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
Список матч
AD9725 Datasheet PDF : 16 Pages
| |||
Preliminary Technical Data
SDO
Serial data out. Data is read from this pin for protocols that use
separate lines for transmitting and receiving data. In the case
where the AD9725 operates in a single bidirectional I/O mode,
this pin does not output data and is set to a high impedance
state.
MSB/LSB Transfers
The AD9725 serial port can support both MSB first and LSB
first data formats. This functionality is controlled by register
address 00h Bit 6. The default is MSB first. When this bit is set
to active high, the AD9725 serial port is in LSB first format.
That is, if the AD9725 is in LSB first mode, the instruction byte
must be written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address of
the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB first mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.
The AD9725 serial port controller address will increment from
1Fh to 00h for multibyte I/O operations if the MSB first mode is
active. The serial port controller address will decrement from
00h to 1Fh for multibyte I/O operations if the LSB first mode is
active.
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
R/W 16(n) 15(n) 14
13 12 11
10 D7n D6n
D7n D6n
D20 D10 D00
D20 D10 D00
Figure 9. Serial Register Interface Timing MSB First
AD9725
NOTES ON SERIAL PORT OPERATION
The AD9725 serial port configuration bits reside in Bit 6 and
Bit 7 of register address 00h. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of communication cycle. Care
must be taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
10 11 12 13
14 15(n) 16(n) R/W D00 D10 D20
D00 D10 D20
D6n D7n
D6n D7n
Figure 10. Serial Register Interface Timing LSB First
CS
SCLK
SDIO
tDS
tSCLK
tPWH
tPWL
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 11. Timing Diagram for Register Write to AD9725
CS
SCLK
SDIO
SDO
DATA BIT n
tDV
DATA BIT n– 1
Figure 12. Timing Diagram for Register READ to AD9725
The same considerations apply to setting the reset bit in register
address 00h. All other registers are set to their default values, but
the software reset doesn’t affect the bits in register address 00h.
It is recommended to use only single byte transfers when
changing serial port configurations or initiating a software
reset.
Rev. PrA | Page 15 of 16
Share Link: 