AD9645BCPZRL7-80(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD9645BCPZRL7-80
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9645BCPZRL7-80 Datasheet PDF : 36 Pages
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AD9645
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Input Clock Rate
Conversion Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Lane Delay (tLD)
Data-to-Data Skew (tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)5
Pipeline Latency
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
APERTURE
Aperture Delay (tA)
25°C
Aperture Uncertainty (Jitter, tJ)
25°C
Out-of-Range Recovery Time
25°C
Min
10
10
1.5
(tSAMPLE/16) − 300
(tSAMPLE/16) − 300
Typ
6.25/4.00
6.25/4.00
2.3
300
300
2.3
tFCO + (tSAMPLE/16)
tSAMPLE/16
tSAMPLE/16
90
±50
250
375
16
Max
1000
80/125
3.1
(tSAMPLE/16) + 300
(tSAMPLE/16) + 300
±200
1
174
1
Unit
MHz
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ps
ns
μs
Clock
cycles
ns
fs rms
Clock
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.
5 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
See Figure 68
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge (not shown in Figure 68)
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge (not shown in Figure 68)
Limit
2
2
40
2
2
10
10
10
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Rev. 0 | Page 6 of 36
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