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AD9637BCPZRL7-80

Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AVDD 1

VIN+ G 2

VIN– G 3

AVDD 4

VIN– H 5

VIN+ H 6

AVDD 7

AVDD 8

CLK– 9

CLK+ 10

AVDD 11

AVDD 12

DNC 13

DRVDD 14

D– H 15

D+ H 16

AD9637

TOP VIEW

(Not to Scale)

48 AVDD

47 VIN+ B

46 VIN– B

45 AVDD

44 VIN– A

43 VIN+ A

42 AVDD

41 PDWN

40 CSB

39 SDIO/DFS

38 SCLK/DTP

37 AVDD

36 DNC

35 DRVDD

34 D+ A

33 D– A

AD9637

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

Figure 5. Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

0, EP

AGND,

Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the

Exposed Pad analog ground for the part. This exposed pad must be connected to analog ground for proper operation.

1, 4, 7, 8, 11,

12, 37, 42, 45,

48, 51, 59, 62

AVDD

1.8 V Analog Supply.

13, 36

DNC

Do Not Connect. Do not connect to this pin.

14, 35

DRVDD

1.8 V Digital Output Driver Supply.

2, 3

VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement.

5, 6

VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True.

9, 10

CLK−, CLK+

Input Clock Complement, Input Clock True.

15, 16

D− H, D+ H

ADC H Digital Output Complement, ADC H Digital Output True.

17, 18

D− G, D+ G

ADC G Digital Output Complement, ADC G Digital Output True.

19, 20

D− F, D+ F

ADC F Digital Output Complement, ADC F Digital Output True.

21, 22

D− E, D+ E

ADC E Digital Output Complement, ADC E Digital Output True.

23, 24

DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True.

25, 26

FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True.

27, 28

D− D, D+ D

ADC D Digital Output Complement, ADC D Digital Output True.

29, 30

D− C, D+ C

ADC C Digital Output Complement, ADC C Digital Output True.

31, 32

D− B, D+ B

ADC B Digital Output Complement, ADC B Digital Output True.

33, 34

D− A, D+ A

ADC A Digital Output Complement, ADC A Digital Output True.

38

SCLK/DTP

Serial Clock (SCLK)/Digital Test Pattern (DTP).

39

SDIO/DFS

Serial Data Input/Output (SDIO)/Data Format Select (DFS).

40

CSB

Chip Select Bar.

41

PDWN

Power-Down.

43, 44

VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement.

46, 47

VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True.

49, 50

VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement.

Rev. A | Page 9 of 40

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