AD9637BCPZRL7-40(Rev0) Просмотр технического описания (PDF) - Analog Devices

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AD9637BCPZRL7-40
(Rev.:Rev0)

Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

Analog Devices 

Data Sheet

AD9637

Timing Diagrams

N–1

VIN± x

CLK–

tA

tEH

N

tEL

CLK+

DCO–

DCO+

FCO–

FCO+

D– x

D+ x

tCPD

tFCO

tFRAME

tPD

tDATA

MSB D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 MSB D10

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16

Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)

N–1

VIN± x

CLK–

tA

tEH

N

tEL

CLK+

DCO–

tCPD

DCO+

FCO–

tFCO

tFRAME

FCO+

D– x

D+ x

tPD

tDATA

MSB D8

D7 D6

D5

D4 D3

D2

D1 D0 MSB D8

D7 D6

D5

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16

Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode

CLK+

SYNC

tSSYNC

tHSYNC

Figure 4. SYNC Input Timing Requirements

Rev. 0 | Page 7 of 40

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