AD9637BCPZRL7-80(Rev0) Просмотр технического описания (PDF) - Analog Devices

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AD9637BCPZRL7-80
(Rev.:Rev0)

Octal, 12-Bit, 40/80 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

Analog Devices 

Data Sheet

AD9637

CROSSTALK

Crosstalk (Overrange Condition)2

ANALOG INPUT BANDWIDTH, FULL POWER

AD9637-40

25°C

−98

25°C

−89

25°C

650

AD9637-80

−96

dB

−89

dB

650

MHz

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2 Overrange condition is specified with 3 dB of the full-scale input range.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 3.

Parameter1

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Differential Input Voltage2

Input Voltage Range

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

LOGIC INPUT (SDIO)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

LOGIC OUTPUT (SDIO)3

Logic 1 Voltage (IOH = 800 μA)

Logic 0 Voltage (IOL = 50 μA)

DIGITAL OUTPUTS (D± x), ANSI-644

Logic Compliance

Differential Output Voltage (VOD)

Output Offset Voltage (VOS)

Output Coding (Default)

DIGITAL OUTPUTS (D± x), LOW POWER,

REDUCED SIGNAL OPTION

Logic Compliance

Differential Output Voltage (VOD)

Output Offset Voltage (VOS)

Output Coding (Default)

Temp Min

Full

0.2

Full

AGND − 0.2

Full

25°C

25°C

Full

1.2

Full

0

25°C

25°C

Full

1.2

Full

0

25°C

25°C

Full

1.2

Full

0

25°C

25°C

Full

Full

Full

247

Full

1.13

Typ

Max

CMOS/LVDS/LVPECL

3.6

AVDD + 0.2

0.9

15

4

AVDD + 0.2

0.8

30

2

AVDD + 0.2

0.8

26

2

AVDD + 0.2

0.8

26

5

1.79

0.05

LVDS

350

454

1.21

1.38

Twos complement

Full

150

Full

1.13

LVDS

200

250

1.21

1.38

Twos complement

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2 This is specified for LVDS and LVPECL only.

3 This is specified for 13 SDIO/DFS pins sharing the same connection.

Unit

V p-p

V

V

kΩ

pF

V

V

kΩ

pF

V

V

kΩ

pF

V

V

kΩ

pF

V

V

mV

V

mV

V

Rev. 0 | Page 5 of 40

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