AD9516-0(RevC) Просмотр технического описания (PDF) - Analog Devices
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AD9516-0 Datasheet PDF : 80 Pages
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Data Sheet
AD9516-0
TIMING CHARACTERISTICS
Table 5.
Parameter
Min
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution Configuration 835
Clock Distribution Configuration
773
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS1
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
OUT6, OUT7, OUT8, OUT9
For All Divide Values
1.4
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS1
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
1.6
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
DELAY ADJUST3
Shortest Delay Range4
Zero Scale
50
Full Scale
540
Longest Delay Range4
Zero Scale
200
Quarter Scale
1.72
Full Scale
5.7
Delay Variation with Temperature
Short Delay Range5
Zero Scale
Full Scale
Long Delay Range5
Zero Scale
Full Scale
Typ Max Unit
70
180 ps
70
180 ps
995 1180 ps
933 1090 ps
0.8
ps/°C
5
15 ps
13
40
ps
220 ps
170 350 ps
160 350 ps
1.8 2.1
1.25
ns
ps/°C
6
62 ps
25
150 ps
430 ps
495 1000 ps
475 985 ps
2.1 2.6 ns
2.6
ps/°C
4
66 ps
28
180 ps
675 ps
315 680 ps
880 1180 ps
570 950 ps
2.31 2.89 ns
8.0 10.1 ns
0.23
−0.02
0.3
0.24
ps/°C
ps/°C
ps/°C
ps/°C
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
20% to 80%, measured differentially
80% to 20%, measured differentially
See Figure 43
See Figure 45
Termination = 100 Ω differential; 3.5 mA
20% to 80%, measured differentially2
20% to 80%, measured differentially2
Delay off on all outputs
Delay off on all outputs
Termination = open
20% to 80%; CLOAD = 10 pF
80% to 20%; CLOAD = 10 pF
Fine delay off
Fine delay off
LVDS and CMOS
Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 101111b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b
Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 000000b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b
1 This is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Corresponding CMOS drivers set to A for noninverting and B for inverting.
3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
4 Incremental delay; does not include propagation delay.
5 All delays between zero scale and full scale can be estimated by linear interpolation.
Rev. C | Page 7 of 80
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