AD9230-210 Просмотр технического описания (PDF) - Analog Devices

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AD9230-210

12-Bit, 170/210/250 MSPS 1.8 V A/D Converter

Analog Devices 

AD9230

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Preliminary Technical Data

D3- 1

D3+ 2

D4- 3

D4+ 4

D5- 5

D5+ 6

DRVDD 7

DRGND 8

D6- 9

D6+ 10

D7- 11

D7+ 12

D8- 13

D8+ 14

AD9230

56 Lead for

LFCSP

TOP VIEW

(Not to Scale)

Pin 0 (exposed paddle) = AGND

42 AVDD

41 AVDD

40 CML

39 AVDD

38 AVDD

37 AVDD

36 VIN-

35 VIN+

34 AVDD

33 AVDD

32 AVDD

31 RBIAS

30 AVDD

29 PWDN

Figure 3. Pinout )

Table 5. PIN FUNCTION DESCRIPTIONS

Pin Number

Mnemonic Description

30,32,33,34,37,38,39,41, AVDD

42,43,46

1.8 V Analog Supply.

7, 24,47

DRVDD

1.8 V Digital Output Supply.

0

AGND1

Analog Ground.

8, 23,48

DRGND1 Digital Output Ground.

35

VIN+

Analog Input—True.

36

VIN–

Analog Input—Complement.

40

CML

Analog input common mode output pin

44

CLK+

Clock Input—True.

45

CLK–

Clock Input—Complement.

31

RBIAS

Set Pin for Chip Bias Current. (Place 1% X kohm resistor terminated to ground).

28

RESET

Chip Reset ( Active high)

25

SDIO

Serial port input/output pin

26

SCLK

Serial port clock

27

CSB

Serial port chip select (Active low)

29

PWDN

Chip power down

49

DCO–

Data Clock Output—Complement.

50

DCO+

Data Clock Output—True.

51

D0–

D0 Complement Output Bit (LSB).

52

D0+

D0 True Output Bit (LSB).

53

D1–

D1 Complement Output Bit.

1 AGND and DRGND should be tied to a common quiet ground plane.

Rev. PrE | Page 8 of 21

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