AD8389 Просмотр технического описания (PDF) - Analog Devices
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AD8389 Datasheet PDF : 12 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8389
AVSS 1
MONITRI 2
MONITGI 3
MONITBI 4
AVDD 5
AVSS 6
VCONTR 7
AVDD 8
AVSS 9
VCONTG 10
VCONTB 11
AVSS 12
PIN 1
INDICATOR
AD8389
TOP VIEW
(Not to Scale)
48-LEAD LFCSP
7mm × 7mm
36 DXRO
35 ENBX1RO
34 ENBX2RO
33 ENBX3RO
32 ENBX4RO
31 CLXRO
30 DXGO
29 ENBX1GO
28 ENBX2GO
27 ENBX3GO
26 ENBX4GO
25 CLXGO
NC =
NO CONNECT
Figure 3. 48-Lead LFCSP, 7 mm × 7 mm Pin Configuration
Table 3. Pin Function Descriptions
Mnemonic
Function
AVDD, DRVDD Power Supply
AVSS, DRVSS Ground
CLK
Clock
COMPEDGE
Edge Select
SLOW
Delay Select
DXI
CLXI
ENBX(1–4)I
MONITxI
Reference Input
Input
Inputs
Feedback Inputs
DXxO
CLXxO
ENBX(1–4)xO
VCONTx
Delayed Outputs
Delayed Outputs
Delayed Outputs
Control Voltage
Description
Power Supply.
Ground.
Clock Input. Active edge is the rising edge.
When set HIGH, the phase detector compares the falling edge of DXIN with the rising edge of
MONITxI. When set LOW, the phase detector compares the rising edge of DXIN with the falling
edge of MONITxI.
When set HIGH and COMPEDGE = HIGH, the delay between the falling edges of DXI and the
rising edges of MONITI is maintained at 9/(fCLK) + t4. The delay is maintained at 26/(fCLK) + t4 when
COMPEDGE = LOW. When set LOW and COMPEDGE = HIGH, the delay between the falling edges
of DXI and the rising edges of MONITI is maintained at 15/(fCLK) + t4. The delay is maintained at
32/(fCLK) + t4 with COMPEDGE = LOW.
LCD Timing Input from the Image Processor. Used as the input to all phase detectors.
LCD Timing Input from the Image Processor.
LCD Timing Inputs from the Image Processor.
Inputs from the LCD. Used as the feedback input to each phase detector. When the AD8389
forms part of a closed loop, it maintains a constant delay between the DXI input and this
reference input pin.
200 pF capacitors connected between these pins and the AVSS plane are required for proper
operation of the internal charge pump.
Rev. 0 | Page 5 of 12
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