AD8384 Просмотр технического описания (PDF) - Analog Devices

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AD8384

10-Bit, 6-Channel Decimating LCD DecDriver® with Level Shifters

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8384

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

DGND 1

TSTM 2

CLK 3

XFR 4

STSQ 5

INV 6

R/L 7

E/O 8

SDI 9

SEN 10

SCL 11

NC 12

AGNDS 13

SVRL 14

SVRH 15

VAO1 16

VAO2 17

AVCCS 18

DIRXIN 19

DIRYIN 20

PIN 1

IDENTIFIER

AD8384

TOP VIEW

(Not to Scale)

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

60 AGND0

59 VID0

58 AVCC0,1

57 VID1

56 AGND1,2

55 VID2

54 AVCC2,3

53 VID3

52 AGND3,4

51 VID4

50 AVCC4,5

49 VID5

48 AGND5

47 CLXN

46 CLX

45 ENBX4

44 ENBX3

43 ENBX2

42 ENBX1

41 DX

NC =

NO CONNECT

Figure 3. 80-Lead 12 mm × 12 mm TQFP E-Pad Pin Configuration

Table 7. Pin Function Descriptions

Pin Name

Function

Description

DB(0:9)

Data Input

10-Bit Data Input. MSB = DB(9).

CLK

Clock

Clock Input.

STSQ

Start Sequence

The state of STSQ is detected on the active edge of CLK. A new data loading sequence

begins on the next active edge of CLK after STSQ is detected HIGH.

The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when

E/O is held LOW.

R/L

Right/Left Select

A new data loading sequence begins on the left, with Channel 0, when this input is LOW,

and on the right, with Channel 5, when this input is HIGH.

E/O

Even/Odd Select

The active CLK edge is the rising edge when this input is held HIGH. It is the falling edge

when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when

this input is HIGH and on the falling edges when this input is LOW.

XFR

Data Transfer

XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held

HIGH. Data is transferred to the video outputs on the next rising CLK edge after XFR is

detected.

VID0–VID5

Analog Outputs

These pins are directly connected to the analog inputs of the LCD panel.

V1, V2

Reference Voltages

The voltage applied between V1 and AGND sets the white video level during INV = LOW.

The voltage applied between V2 and AGND sets the white video level during INV = HIGH.

VRH, VRL

Full-Scale References Twice the voltage applied between these pins sets the full-scale video output voltage.

BYP

Bypass

A 0.1µ F capacitor connected between this pin and AGND ensures optimum settling time.

Rev. 0 | Page 9 of 24

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